발간년도 : [2017]
| 논문정보 |
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| 논문명(한글) |
[Vol.12, No.3] Design of Two-times Faster Bit-Serial Multiplier Using Normal Basis of GF(2m) |
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| 논문투고자 |
Yong-Suk Cho, Kyoung-Il Min |
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| 논문내용 |
Finite field arithmetic has recently gained growing attention due to its wide range of applications in signal processing, error control coding and especially in cryptography. In these applications, there is a need to design low complexity finite field arithmetic units. One important factor that could greatly affect computation performance is the basis in which finite field elements are represented. Among the basis, representation of fields elements using a normal basis is quite attractive for hardware implementation since the squaring operation over GF(2m) can be performed by only one-bit cyclic shift to left. In this paper, we propose a new architecture of two-times faster bit-serial finite field multiplier using a normal basis. In the proposed multiplier, the bits of an operand are grouped into the two parts and each part is implemented simultaneously by bit-serial multiplier. Therefore, the proposed multiplier takes [m/2] clock cycles, to finish one multiplication operation in a binary field of size m. The proposed architecture is two-times faster than bit-serial architectures but with lower area complexity than bit-parallel ones. It is shown that the new design has higher regular architecture compared to other similar proposals and therefore, well-suited for VLSI implementation. The main advantage of the proposed architecture is that a trade-off between hardware complexity and delay time can be achieved. Therefore, the proposed multipliers are more suitable for resource constrained cryptographic systems where the value of m is large but space is of concern. |
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